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Trigger and Data Acquisition (DAQ) for the Linear Collider Detector was discussed at a series of workshops of the second ECFA/DESY Linear Collider Study and a deadtime free "Software Trigger" was proposed as outlined below.
Due to cross sections for the various physics processes differing by several orders of magnitude, highly efficient and flexible event selection and data acquisition (DAQ) are essential. The bunched operation modes of all LC designs have the common feature of a 3-order-of-magnitude longer time between bunch trains than the bunch-to-bunch separation. The Telsa bunch structure as an example is shown here, This suggests using the time between trains for the hardware-trigger-free and deadtime-free readout of all data generated during a whole train. Subsequent software event selection ("software trigger") using a type of filter farm will then analyse the full data to achieve the highest possible efficiency and flexibility.
All present LC detector designs are therefore based on a software trigger with the following assumptions :
- dead time free pipeline during a bunch train,
- no hardware trigger,
- frontend pipeline with capacity for storing data from a complete train,
- event selection by software.
The frontend of the subdetectors should be equipped with hit detection/zero suppression capability and readout channel multiplexing into a common readout line. Although the DAQ system for the LC detector is more relaxed than for LHC experiments, the frontend readout systems for the high granularity detectors impose demands sometimes beyond those for LHC, both for electronic integration and power consumption. This necessitates R&D for the frontend readout which must be covered by the specific subdetector groups. For the overall event building, proof of concept and the development of event selection strategies will require event-builder prototyping as well.
For the subdetectors the large number of readout channels demand development of high electronic integration and smallest possible power dissipation to reduce cooling needs, reduce dead space for the readout electronics and readout cables at the detector, achieve manageable data rates for the high granularity systems by online zero suppression, hit detection and data processing, and allow online monitoring and calibration of all frontend readout channels.
The central DAQ system itself will use commercial products available by the time it is built, and therefore no specific R&D for central DAQ hardware is warrented at this time. However for various test systems, a DAQ prototype should be provided which is based on today's commercial products. The only part of the central DAQ system needing hardware R&D is the common interface of the frontend readout systems to the central DAQ system. This common interface has to be specified and designed in close cooperation with the different detector R&D groups in order to ensure a unique interface or at least a small set of standardized interfaces for all subdetectors.
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Introduction
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