; Filename: CMB_Test.asm ; Date: 24.01.2005 ; Author: R. van Staa ; Company: Uni Hamburg ; Update: 09.02.05: Identifier Definition changed ; LED Register Reset at Power on ;******************************************************************* ; ; Files required: P18F448.inc ; ;******************************************************************* ; LIST P=18F448, F=INHX32 #include ; ;******************************************************************* ; ; Configuration Bits are defined in MPLAB IDE ; ; CAN Receive Identifier: $500 + 2* BAD ; CAN Functions: ; Function 1: Command: Set LED (12 Bit) ; SubFunction 1: Set LED ; 1.Byte: $11 ; 2.Byte: LED Value low ; 3.Byte: LED Value high ; Function 9: Response to Function 1: ; 1.Byte: SubFunction Nr. ; ; Function 2: Set DAC Values ; SubFunction 1: Set DAC A ; 1.Byte: $21 ; 2.Byte: DAC Value ; ; SubFunction 2: Set DAC B ; 1.Byte: $22 ; 2.Byte: DAC Value ; ; SubFunction 3: Set DAC A and DAC B ; 1.Byte: $23 ; 2.Byte: DAC Value ; ; Function 10: Response to Function 2: ; 1.Byte: SubFunction Nr. ; ; Function 3: Write ADC Control Registers ; SubFunction 1: Write Mode Register ; 1.Byte: $31 ; 2.Byte: Data Byte low ; 3.Byte: Data Byte high ; SubFunction 2: Write Configuration Register ; 1.Byte: $32 ; 2.Byte: Data Byte low ; 3.Byte: Data Byte high ; SubFunction 3: Write Offset Register ; 1.Byte: $33 ; 2.Byte: Data Byte low ; 3.Byte: Data Byte high ; SubFunction 4: Write Full-Scale Register ; 1.Byte: $34 ; 2.Byte: Data Byte low ; 3.Byte: Data Byte high ; SubFunction 5: Write Time Interval (sec) ; 1.Byte: $35 ; 2.Byte: Time Interval ; SubFunction 6: Reset ADC ; 1.Byte: $36 ; Function 11: Response to Function 3: ; 1.Byte: SubFunction Nr. ; ; Function 4: Read ADC Control Registers ; SubFunction 1: Read Status Register (8 Bit) ; 1.Byte: $41 ; SubFunction 2: Read Mode Register (16 Bit) ; 1.Byte: $42 ; SubFunction 3: Read Configuration Register (16 Bit) ; 1.Byte: $43 ; SubFunction 4: Read ID Register (8 Bit) ; 1.Byte: $44 ; SubFunction 5: Read Offset Register (16 Bit) ; 1.Byte: $45 ; SubFunction 6: Read Full-Scale Register (16 Bit) ; 1.Byte: $46 ; SubFunction 7: Read Time Interval (8 Bit) ; 1.Byte: $47 ; Function 12: Response to Function 4: ; 1.Byte: SubFunction Nr. ; 2.Byte: Data Byte low ; 3.Byte: Data Byte high (if neccessary) ; ; Function 5: Read ADC Measurement ; SubFunction 1: Read Channel 0 and 1 ; 1.Byte: $51 ; SubFunction 2: Read Channel 2 and 3 ; 1.Byte: $52 ; SubFunction 3: Read Channel 4 and 5 ; 1.Byte: $53 ; SubFunction 4: Read Channel 6 and 7 ; 1.Byte: $54 ; SubFunction 5: Read Channel 8 and 9 ; 1.Byte: $55 ; SubFunction 6: Read Channel 10 and 11 ; 1.Byte: $56 ; SubFunction 7: Read Channel 12 and 13 ; 1.Byte: $57 ; SubFunction 8: Read Channel 14 and 15 ; 1.Byte: $58 ; Function 13: Response to Function 5: ; 1.Byte: SubFunction Nr. ; 2.Byte: Status Channel n ; 3.Byte: Data Byte low, Channel n ; 4.Byte: Data Byte high,Channel n ; 5.Byte: Status Channel n+1 ; 6.Byte: Data Byte low, Channel n+1 ; 7.Byte: Data Byte high,Channel n+1 ;; ; Function 6: Read Status ; SubFunction 1: Read CAN Error Bytes ; 1.Byte: $61 ; SubFunction 2: Read Firmware Release Number ; 1.Byte: $62 ; Function 14: Response to Function 6: ; SubFunction 1: 1.Byte: $61 ; 2.Byte: CAN Error Status ; 3.Byte: Transmit Error Counter ; 4.Byte: Receive Error Counter ; SubFunction 2: 1.Byte: $62 ; 2.Byte: Bits V15..V8 of Release Number ; 3.Byte: Bits V7..V0 of Release Number ; ; Function 15: Periodic Messages of ADC Measurement ; Argument Nr.n: 1.Byte: $F0+n (1 <= n <= 8) ; 2.Byte: Status Channel 2n-1 ; 3.Byte: Data Byte low, Channel 2n-1 ; 4.Byte: Data Byte high,Channel 2n-1 ; 5.Byte: Status Channel 2n ; 6.Byte: Data Byte low, Channel 2n ; 7.Byte: Data Byte high,Channel 2n ;******************************************************************* ; Variabale Definition CBLOCK 0x000 TYPENR ; Type Number INSTNR ; Instance Number FUNCNR ; Function Number OPREG ; Operation Register OPREG1 ; Operation Register BITCNT ; Bit Counter BYTEFLAG SHIFTREG ; Shift Register SHIFTREGL SHIFTREGH RECBYTE0 ; Argument Byte of Request Function RECBYTE1 ; Argument Byte of Request Function RECBYTE2 ; Argument Byte of Request Function RECBYTE3 ; Argument Byte of Request Function DACCONTR ; DAC Control Register DACVALUE ; DAC Value 0 <= DV <= 255 VERSHIGH ; Firmware Version High Byte VERSLOW ; Firmware Version Low Byte ADCSTAT ; ADC Status Byte MODEREGL ; ADC Mode Register MODEREGH CONFREGL ; ADC Configuration Register CONFREGH ADC0L ; ADC Value, Channel 0 ADC0H ADC1L ; ADC Value, Channel 1 ADC1H ADC2L ; ADC Value, Channel 2 ADC2H ADC3L ; ADC Value, Channel 3 ADC3H ADC4L ; ADC Value, Channel 4 ADC4H ADC5L ; ADC Value, Channel 5 ADC5H ADC6L ; ADC Value, Channel 6 ADC6H ADC7L ; ADC Value, Channel 7 ADC7H ADC8L ; ADC Value, Channel 8 ADC8H ADC9L ; ADC Value, Channel 9 ADC9H ADC10L ; ADC Value, Channel 10 ADC10H ADC11L ; ADC Value, Channel 11 ADC11H ADC12L ; ADC Value, Channel 12 ADC12H ADC13L ; ADC Value, Channel 13 ADC13H ADC14L ; ADC Value, Channel 14 ADC14H ADC15L ; ADC Value, Channel 15 ADC15H ASTAT0 ; ADC Status Channel 0 ASTAT1 ; ADC Status Channel 1 ASTAT2 ; ADC Status Channel 2 ASTAT3 ; ADC Status Channel 3 ASTAT4 ; ADC Status Channel 4 ASTAT5 ; ADC Status Channel 5 ASTAT6 ; ADC Status Channel 6 ASTAT7 ; ADC Status Channel 7 ASTAT8 ; ADC Status Channel 8 ASTAT9 ; ADC Status Channel 9 ASTAT10 ; ADC Status Channel 10 ASTAT11 ; ADC Status Channel 11 ASTAT12 ; ADC Status Channel 12 ASTAT13 ; ADC Status Channel 13 ASTAT14 ; ADC Status Channel 14 ASTAT15 ; ADC Status Channel 15 MUX ; Multiplexer Address MUXSET ; Flag, that MUX has been set TCOUNT ; Timer Count (sec) PERIOD ; Period for Message Transmission ENDC ; Reset Vector ORG 0x000 goto Main ; goto CANSERV ; Main Program ORG 0x010 Main: ; ADC Registers movlw 0x00 ; Mode Register movwf MODEREGH movlw 0x0F movwf MODEREGL movlw 0x10 ; Configuration Register movwf CONFREGH movlw 0x80 movwf CONFREGL ; Store Firmware Release Number movlw 0x52 movwf VERSHIGH movlw 0x09 movwf VERSLOW ; Configure Controller Registers movlw 0x00 movwf INTCON,0 ; Disable all Interrupts movlw 0x1F movwf RCON ; Disable all Reset Flags movlw 0x07 movwf ADCON1 ; All Ports are digital Ports movlw 0xFF movwf TRISA,0 ; Port A as Input ; RA0: Instance Bit A0 ; RA1: Instance Bit A1 ; RA2: Instance Bit A2 ; RA3: Instance Bit A3 ; RA4: Instance Bit A4 ; RA5: Instance Bit A5 movlw 0xFB movwf TRISB ; Port B ; RB0: CAN Mode (I) ; RB1: SEL1 (I) ; RB2: CAN TX (O) ; RB3: CAN RX (I) ; RB5: SEL2 (I) ; RB6: PGC (I) ; RB7: PGD (I) movlw 0x0 movwf TRISC ; Port C as Output ; RC0: /ADCSEL (O) ; RC1: /DACSEL (O) ; RC2: MUXSEL (O) ; RC3: CS4 (O) ; RC4: AX0 (O) Multipl Addr Bits ; RC5: AX1 (0) ; RC6: AX2 (0) ; RC7: AX3 (O) bsf LATC,0,0 ; /ADCSEL = 1 bsf LATC,1,0 ; /DACSEL = 1 bcf LATC,2,0 ; MUXSEL = 0 bcf LATC,3,0 ; CS4 = 0 movlw 0xFF movwf TRISD,0 ; Port D as Input ; RD0: D0 (O) LED Selection ; RD1: D1 (O) ; RD2: D2 (O) ; RD3: D3 (O) ; RD4: D4 (O) ; RD5: D5 (O) ; RD6: D6 (O) ; RD7: D7 (O) movlw 0x1 movwf TRISE ; Port E ; RE0: DOUT (I) Ser.Data from ADC ; RE1: DIN (O) Ser.Data to ADC + DAC ; RE2: SCLK (O) Ser.Clock bcf LATE,2,0 ; Ser. Clock = 0 movlw 0x07 movwf CMCON ; Disable Comparators movlw 0x48 movwf T0CON ; Timer0: 8 bit, no PreScaler, 1 MHz ; Configure Identifier ; $500 + 2*BAD (Board Address movff PORTA,INSTNR movlw 0x3F andwf INSTNR,1,0 ; Store RA5..RA0 as Board Address ; Configure CAN Registers movlw 0x20 movwf CIOCON ; CANTX will drive VDD, when recessive clrf PIE3 ; Disable all CAN Interrupts movlw 0x0F movwf BSR ; Select Bank #15 movlw 0x03 movwf TXB0CON,1 ; TX Buffer0 Priority: High movlw 0x02 movwf TXB1CON,1 ; TX Buffer1 Priority: Medium movlw 0x01 movwf TXB2CON,1 ; TX Buffer2 Priority: Low movff INSTNR,OPREG ;Construct Receive Filter rrncf OPREG,1,0 rrncf OPREG,1,0 movlw 0x0F andwf OPREG,1,0 ;BAD5..BAD2 in OPREG movlw 0xA0 iorwf OPREG,1,0 movff OPREG,RXF0SIDH movff RXF0SIDH,RXF1SIDH movff INSTNR,OPREG movlw 0x03 andwf OPREG,1,0 ;Mask BAD1..BAD0 rlncf OPREG,1,0 ; Shift left 6 times rlncf OPREG,1,0 rlncf OPREG,1,0 rlncf OPREG,1,0 rlncf OPREG,1,0 rlncf OPREG,1,0 movff OPREG,RXF0SIDL movff RXF0SIDL,RXF1SIDL movff RXF0SIDH,TXB0SIDH ; copy to Standard Identifier movff RXF0SIDL,TXB0SIDL bsf TXB0SIDL,5,1 ; Set ID0 for Transmit Ident. ; Parameters for TX Buffer 1,2 not set movlw 0x24 ; Rollover, Filter: RXF0 movwf RXB0CON,1; ; Accept only Standard Identifier movlw 0xE0 ; Filter: RXF0 movwf RXB1CON,1; ; Accept only Standard Identifier movlw 0xFF movwf RXM0SIDH,1 ; Mask: Mask Filter Bits 10..3 movlw 0xE0 movwf RXM0SIDL,1 movlw 0x00 movwf BRGCON1,1 ; Set Prescaler to 1/2 (Fosc = 4 MHz) movlw 0xAA movwf BRGCON2,1 ; Set Baud Rate to 125 khz movlw 0x05 movwf BRGCON3,1 clrf CANCON ; Switch to Normal Mode clrf SHIFTREG,0 ; Switch off all LED's call SHIFT0 ; Shift out clrf SHIFTREG ; LED Value low call SHIFT0 ; Shift out bsf LATE,2,0 ; Ser. Clock = 1 (Clock Nr. 17) bcf LATE,2,0 ; Ser. Clock = 0 bsf LATC,3,0 ; CS4 = 1, Store in Output Reg. bcf LATC,3,0 ; CS4 = 0 call RESETADC ; Reset ADC movlw 0x83 ; Configure Timer 0: movwf T0CON ; 16 Bit, 4 Bit PreScaler movlw 0xFF movwf TMR0H movlw 0x00 movwf TMR0L clrf TCOUNT movlw 0x00 movwf PERIOD clrf MUX ; MUX Address = 0 clrf MUXSET ; MUX Address = 0 ;Main Loop LOOP: btfsc PORTB,5,0 ; Check if Test Mode (Bit0 = 0 ) bra LOOP1 movff PORTA,SHIFTREG ; Test Mode call SHIFT0 ; Shift out movff PORTD,SHIFTREG ; call SHIFT0 ; Shift out bsf LATE,2,0 ; Ser. Clock = 1 (Clock Nr. 17) bcf LATE,2,0 ; Ser. Clock = 0 bsf LATC,3,0 ; CS4 = 1, Store in Output Reg. bcf LATC,3,0 ; CS4 = 0 goto LOOP LOOP1 btfsc PIR3,0,1 ; Test CAN receive buffer 0 call CANSERV ; Branch, if Bit 0 is set btfsc INTCON,2,1 ; Test Timer Flag call TIMERINT ; Timer Interrupt bsf LATE,2,0 ; Ser. Clock = 1 bcf LATC,0,0 ; /ADCSEL = 0 btfsc PORTE,0,0 ; If Conversion Compl. goto LOOP2 goto LOOP LOOP2 nop Tstfsz MUXSET ; Read ADC Data, if MUXSET=0 bra ADR movlw 0x58 ; Read ADC Data movwf SHIFTREG bsf BYTEFLAG,0,0 ; two Bytes call RADC1 ; Read ADC data bra ADR0 ADR movlw 0x58 ; Read ADC Data movwf SHIFTREG bsf BYTEFLAG,0,0 ; two Bytes call RADC1 ; Dummy Read clrf MUXSET goto LOOP ADR0 movlw 0x00 Cpfseq MUX bra ADR1 movff SHIFTREGL,ADC0L movff SHIFTREGH,ADC0H movff ADCSTAT,ASTAT0 ; Build Status Byte movf MUX,0,0 iorwf ASTAT0,1 bra ADR16 ADR1 movlw 0x01 Cpfseq MUX bra ADR2 movff SHIFTREGL,ADC1L movff SHIFTREGH,ADC1H movff ADCSTAT,ASTAT1 ; Build Status Byte movf MUX,0,0 iorwf ASTAT1,1 bra ADR16 ADR2 movlw 0x02 Cpfseq MUX bra ADR3 movff SHIFTREGL,ADC2L movff SHIFTREGH,ADC2H movff ADCSTAT,ASTAT2 ; Build Status Byte movf MUX,0,0 iorwf ASTAT2,1 bra ADR16 ADR3 movlw 0x03 Cpfseq MUX bra ADR4 movff SHIFTREGL,ADC3L movff SHIFTREGH,ADC3H movff ADCSTAT,ASTAT3 ; Build Status Byte movf MUX,0,0 iorwf ASTAT3,1 bra ADR16 ADR4 movlw 0x04 Cpfseq MUX bra ADR5 movff SHIFTREGL,ADC4L movff SHIFTREGH,ADC4H movff ADCSTAT,ASTAT4 ; Build Status Byte movf MUX,0,0 iorwf ASTAT4,1 bra ADR16 ADR5 movlw 0x05 Cpfseq MUX bra ADR6 movff SHIFTREGL,ADC5L movff SHIFTREGH,ADC5H movff ADCSTAT,ASTAT5 ; Build Status Byte movf MUX,0,0 iorwf ASTAT5,1 bra ADR16 ADR6 movlw 0x06 Cpfseq MUX bra ADR7 movff SHIFTREGL,ADC6L movff SHIFTREGH,ADC6H movff ADCSTAT,ASTAT6 ; Build Status Byte movf MUX,0,0 iorwf ASTAT6,1 bra ADR16 ADR7 movlw 0x07 Cpfseq MUX bra ADR8 movff SHIFTREGL,ADC7L movff SHIFTREGH,ADC7H movff ADCSTAT,ASTAT7 ; Build Status Byte movf MUX,0,0 iorwf ASTAT7,1 bra ADR16 ADR8 movlw 0x08 Cpfseq MUX bra ADR9 movff SHIFTREGL,ADC8L movff SHIFTREGH,ADC8H movff ADCSTAT,ASTAT8 ; Build Status Byte movf MUX,0,0 iorwf ASTAT8,1 bra ADR16 ADR9 movlw 0x09 Cpfseq MUX bra ADR10 movff SHIFTREGL,ADC9L movff SHIFTREGH,ADC9H movff ADCSTAT,ASTAT9 ; Build Status Byte movf MUX,0,0 iorwf ASTAT9,1 bra ADR16 ADR10 movlw 0x0A Cpfseq MUX bra ADR11 movff SHIFTREGL,ADC10L movff SHIFTREGH,ADC10H movff ADCSTAT,ASTAT10 ; Build Status Byte movf MUX,0,0 iorwf ASTAT10,1 bra ADR16 ADR11 movlw 0x0B Cpfseq MUX bra ADR12 movff SHIFTREGL,ADC11L movff SHIFTREGH,ADC11H movff ADCSTAT,ASTAT11 ; Build Status Byte movf MUX,0,0 iorwf ASTAT11,1 bra ADR16 ADR12 movlw 0x0C Cpfseq MUX bra ADR13 movff SHIFTREGL,ADC12L movff SHIFTREGH,ADC12H movff ADCSTAT,ASTAT12 ; Build Status Byte movf MUX,0,0 iorwf ASTAT12,1 bra ADR16 ADR13 movlw 0x0D Cpfseq MUX bra ADR14 movff SHIFTREGL,ADC13L movff SHIFTREGH,ADC13H movff ADCSTAT,ASTAT13 ; Build Status Byte movf MUX,0,0 iorwf ASTAT13,1 bra ADR16 ADR14 movlw 0x0E Cpfseq MUX bra ADR15 movff SHIFTREGL,ADC14L movff SHIFTREGH,ADC14H movff ADCSTAT,ASTAT14 ; Build Status Byte movf MUX,0,0 iorwf ASTAT14,1 bra ADR16 ADR15 movlw 0x0F Cpfseq MUX bra ADR16 movff SHIFTREGL,ADC15L movff SHIFTREGH,ADC15H movff ADCSTAT,ASTAT15 ; Build Status Byte movf MUX,0,0 iorwf ASTAT15,1 ADR16 incf MUX ; Increment MUX Address movlw 0x10 cpfslt MUX,0 clrf MUX,0 ; If MUX >= 16, then MUX=0 movff MUX,OPREG ; Build MUX Address rlncf OPREG,1,0 rlncf OPREG,1,0 rlncf OPREG,1,0 rlncf OPREG,1,0 ; MUX Address = RC4..RC7 bsf OPREG,1,0 ; /CS2 = 1 bsf OPREG,2,0 ; CS3 = 1 movff OPREG,LATC ; Set Multiplexer setf MUXSET goto LOOP ;************************ Subroutines ************************************ TIMERINT: ; Timer Flag has been set. ; Resets Timer Flag, restarts Timer bcf INTCON,2,1 ; Reset Timer Flag movlw 0x0B ; Time Interval: 1 sec movwf TMR0H movlw 0xDB movwf TMR0L incf TCOUNT movf PERIOD,0,0 ; PERIOD -> W cpfslt TCOUNT ; Return, if TCOUNT < PERIOD bra TIM1 return TIM1 clrf TCOUNT Tstfsz PERIOD ; If PERIOD>0, send Message bra SENDM return SENDM: movlw 0x07 movwf TXB0DLC,1 ; Data Length Code movlw 0xF1 movwf TXB0D0 ; Store Data in Transmit Buffer movff ASTAT0,TXB0D1 movff ADC0L,TXB0D2 movff ADC0H,TXB0D3 movff ASTAT1,TXB0D4 movff ADC1L,TXB0D5 movff ADC1H,TXB0D6 bsf TXB0CON,3,1 ; Start Transmission SEND2 btfss TXB0CON,3,1 ; Wait until Transmission complete bra SD2 btfsc INTCON,2,1 ; Test Timer Flag bra TIMEOUT ; Time out after 1 sec bra SEND2 SD2 movlw 0xF2 movwf TXB0D0 ; Store Data in Transmit Buffer movff ASTAT2,TXB0D1 movff ADC2L,TXB0D2 movff ADC2H,TXB0D3 movff ASTAT3,TXB0D4 movff ADC3L,TXB0D5 movff ADC3H,TXB0D6 bsf TXB0CON,3,1 ; Start Transmission SEND3 btfss TXB0CON,3,1 ; Wait until Transmission complete bra SD3 btfsc INTCON,2,1 ; Test Timer Flag bra TIMEOUT ; Time out after 1 sec bra SEND3 SD3 movlw 0xF3 movwf TXB0D0 ; Store Data in Transmit Buffer movff ASTAT4,TXB0D1 movff ADC4L,TXB0D2 movff ADC4H,TXB0D3 movff ASTAT5,TXB0D4 movff ADC5L,TXB0D5 movff ADC5H,TXB0D6 bsf TXB0CON,3,1 ; Start Transmission SEND4 btfss TXB0CON,3,1 ; Wait until Transmission complete bra SD4 btfsc INTCON,2,1 ; Test Timer Flag bra TIMEOUT ; Time out after 1 sec bra SEND4 SD4 movlw 0xF4 movwf TXB0D0 ; Store Data in Transmit Buffer movff ASTAT6,TXB0D1 movff ADC6L,TXB0D2 movff ADC6H,TXB0D3 movff ASTAT7,TXB0D4 movff ADC7L,TXB0D5 movff ADC7H,TXB0D6 bsf TXB0CON,3,1 ; Start Transmission SEND5 btfss TXB0CON,3,1 ; Wait until Transmission complete bra SD5 btfsc INTCON,2,1 ; Test Timer Flag bra TIMEOUT ; Time out after 1 sec bra SEND5 SD5 movlw 0xF5 movwf TXB0D0 ; Store Data in Transmit Buffer movff ASTAT8,TXB0D1 movff ADC8L,TXB0D2 movff ADC8H,TXB0D3 movff ASTAT9,TXB0D4 movff ADC9L,TXB0D5 movff ADC9H,TXB0D6 bsf TXB0CON,3,1 ; Start Transmission SEND6 btfss TXB0CON,3,1 ; Wait until Transmission complete bra SD6 btfsc INTCON,2,1 ; Test Timer Flag bra TIMEOUT ; Time out after 1 sec bra SEND6 SD6 movlw 0xF6 movwf TXB0D0 ; Store Data in Transmit Buffer movff ASTAT10,TXB0D1 movff ADC10L,TXB0D2 movff ADC10H,TXB0D3 movff ASTAT11,TXB0D4 movff ADC11L,TXB0D5 movff ADC11H,TXB0D6 bsf TXB0CON,3,1 ; Start Transmission SEND7 btfss TXB0CON,3,1 ; Wait until Transmission complete bra SD7 btfsc INTCON,2,1 ; Test Timer Flag bra TIMEOUT ; Time out after 1 sec bra SEND7 SD7 movlw 0xF7 movwf TXB0D0 ; Store Data in Transmit Buffer movff ASTAT12,TXB0D1 movff ADC12L,TXB0D2 movff ADC12H,TXB0D3 movff ASTAT13,TXB0D4 movff ADC13L,TXB0D5 movff ADC13H,TXB0D6 bsf TXB0CON,3,1 ; Start Transmission SEND8 btfss TXB0CON,3,1 ; Wait until Transmission complete bra SD8 btfsc INTCON,2,1 ; Test Timer Flag bra TIMEOUT ; Time out after 1 sec bra SEND8 SD8 movlw 0xF8 movwf TXB0D0 ; Store Data in Transmit Buffer movff ASTAT14,TXB0D1 movff ADC14L,TXB0D2 movff ADC14H,TXB0D3 movff ASTAT15,TXB0D4 movff ADC15L,TXB0D5 movff ADC15H,TXB0D6 bsf TXB0CON,3,1 ; Start Transmission return TIMEOUT: bcf INTCON,2,1 ; Reset Timer Flag movlw 0x0B ; Time Interval: 1 sec movwf TMR0H movlw 0xDB movwf TMR0L bcf TXB0CON,3,1 ; Abort Transmission Request return ;************************************************************************ RESETADC: ; Resets the ADC and sets the ADC Control Registers bsf LATE,2,0 ; Ser. Clock = 1 bcf LATC,0,0 ; /ADCSEL = 0 movlw 0xFF ; Reset ADC movwf SHIFTREG call ADCSHIFTO movlw 0xFF movwf SHIFTREG call ADCSHIFTO movlw 0xFF movwf SHIFTREG call ADCSHIFTO movlw 0xFF movwf SHIFTREG call ADCSHIFTO ; goto ML1 movlw 0x08 ; Write ADC Mode Register movwf SHIFTREG call ADCSHIFTO movff MODEREGH,SHIFTREG call ADCSHIFTO movff MODEREGL,SHIFTREG call ADCSHIFTO movlw 0x48 ; Read ADC Mode Register movwf SHIFTREG bsf BYTEFLAG,0,0 ; two Bytes call RADC1 clrf ADCSTAT ; Clear ADC Status Byte movf MODEREGH,0,0 ; MODEREGH -> W cpfseq SHIFTREGH bsf ADCSTAT,5,0 movf MODEREGL,0,0 ; MODEREGL -> W cpfseq SHIFTREGL bsf ADCSTAT,5,0 ML1 movlw 0x10 ; Write ADC Config. Register movwf SHIFTREG call ADCSHIFTO movff CONFREGH,SHIFTREG call ADCSHIFTO movff CONFREGL,SHIFTREG call ADCSHIFTO movlw 0x50 ; Read ADC Config. Register movwf SHIFTREG bsf BYTEFLAG,0,0 ; two Bytes call RADC1 movf CONFREGH,0,0 ; CONFREGH -> W cpfseq SHIFTREGH bsf ADCSTAT,4,0 movf CONFREGL,0,0 ; CONFREGL -> W cpfseq SHIFTREGL bsf ADCSTAT,4,0 return ;************************************************************************ CANSERV: ; Saves the Argument Number and calls a Subroutine according to Function Number bsf LATC,0,0 ; /ADCSEL = 1 bcf LATE,2,0 ; Ser. Clock = 0 movff RXB0D0,RECBYTE0 ; Store Arguments movff RXB0D1,RECBYTE1 movff RXB0D2,RECBYTE2 movff RXB0D3,RECBYTE3 bcf PIR3,0,1 ; Clear Interrupt Flag bcf RXB0CON,7,0 ; Clear RX Full Flag movff RECBYTE0,FUNCNR ; For Function Test movlw 0xF0 andwf FUNCNR,1,0 movff RECBYTE0,OPREG1 ; For SubFunction Test movlw 0x0F andwf OPREG1,1,0 movlw 0x10 cpfseq FUNCNR ; Test Function Nr.1 bra FUNC2 bra SETLED ; Function: Switch LED's FUNC2 movlw 0x20 Cpfseq FUNCNR ; Test Function Nr.2 bra FUNC3 bra SETDAC ; Function: Set DAC Values FUNC3 movlw 0x30 Cpfseq FUNCNR ; Test Function Nr.3 bra FUNC4 bra WRITEADCCON ; Function: Write ADC Control Reg. FUNC4 movlw 0x40 Cpfseq FUNCNR ; Test Function Nr.4 bra FUNC5 bra READADCCON ; Function: Read ADC Control Reg. FUNC5 movlw 0x50 Cpfseq FUNCNR ; Test Function Nr.5 bra FUNC6 bra READADC ; Function: Read ADC FUNC6 movlw 0x60 Cpfseq FUNCNR ; Test Function Nr.6 return bra STATREAD ; Function: Read Status ;************************************************************************ SETLED: ; Response to Function 1: Switch LED's movlw 0x01 cpfseq OPREG1 ; Test Test SubFunction 1 return movff RECBYTE2,SHIFTREG ;LED Value high call SHIFT0 ; Shift out movff RECBYTE1,SHIFTREG ;LED Value low call SHIFT0 ; Shift out bsf LATE,2,0 ; Ser. Clock = 1 (Clock Nr. 17) bcf LATE,2,0 ; Ser. Clock = 0 bsf LATC,3,0 ; CS4 = 1, Store in Output Reg. bcf LATC,3,0 ; CS4 = 0 movlw 0x01 movwf TXB0DLC,1 ; Data Length Code movff RECBYTE0,TXB0D0 ; Store Data in Transmit Buffer bsf TXB0CON,3,1 ; Start Transmission return ;************************************************************************** SETDAC: ; Response to Function 2: Set DAC Values movff RECBYTE1,DACVALUE movlw 0x01 cpfseq OPREG1 ; Test SubFunction 1 bra DARG2 SDACA: ; Set DAC A movlw 0x03 movwf DACCONTR ; Update DAC A from Sfift Register call SHIFTOUT bra SDACEND DARG2 movlw 0x02 Cpfseq OPREG1 ; Test SubFunction 2 bra DARG3 SDACB: ; Set DAC B movlw 0x07 movwf DACCONTR ; Update DAC B from Shift Register call SHIFTOUT bra SDACEND DARG3 movlw 0x03 Cpfseq OPREG1 ; Test SubFunction 3 return SDACAB: ; Set DAC A and B movlw 0x00 movwf DACCONTR ; Update both DAC's from Shift Register call SHIFTOUT SDACEND: movlw 0x01 movwf TXB0DLC,1 ; Data Length Code movff RECBYTE0,TXB0D0 ; Store Data in Transmit Buffer bsf TXB0CON,3,1 ; Start Transmission return SHIFTOUT: ; Shifts out DAC Control Byte and DAC Data Byte, MSbit first bcf LATC,1,0 ; /DACSEL = 0 movff DACCONTR,SHIFTREG call SHIFT0 movff DACVALUE,SHIFTREG call SHIFT0 bsf LATC,1,0 ; /DACSEL = 1 return SHIFT0: ; Shifts out one Byte, MSBit first movlw 0x08 movwf BITCNT ; 8 Bits to be shifted SHIFT1 rlcf SHIFTREG ; Rotate left through Carry bc SHIFT2 ; Branch if Carra set bcf LATE,1,0 ; Data Bit = 0 bra SHIFT3 SHIFT2 bsf LATE,1,0 ; Data Bit = 1 SHIFT3 bsf LATE,2,0 ; Ser. Clock = 1 bcf LATE,2,0 ; Ser. Clock = 0 decfsz BITCNT bra SHIFT1 return ;************************************************************************* WRITEADCCON: ; Response to Function 3: Write ADC Control Registers movff RECBYTE1,SHIFTREGL ;Store Data Bytes movff RECBYTE2,SHIFTREGH movlw 0x01 cpfseq OPREG1 ; Test SubFunction 1 bra MWAC2 WAC1: ; Write Mode Register movlw 0x08 ; Address of Mode Regsiter bra WAC6 MWAC2 movlw 0x02 Cpfseq OPREG1 ; Test SubFunction 2 bra MWAC3 WAC2: ; Write Configuration Register movlw 0x10 ; Address of Configuration Regsiter bra WAC6 MWAC3 movlw 0x03 Cpfseq OPREG1 ; Test SubFunction 3 bra MWAC4 WAC3: ; Write Offset Register movlw 0x30 ; Address of Offset Regsiter bra WAC6 MWAC4 movlw 0x04 Cpfseq OPREG1 ; Test SubFunction 4 bra MWAC5 WAC4: ; Write Full-Scale Register movlw 0x38 ; Address of Full-Scale Regsiter bra WAC6 MWAC5 movlw 0x05 Cpfseq OPREG1 ; Test SubFunction 5 bra MWAC6 WAC5: ; Set Period Parameter movff RECBYTE1,PERIOD bra WAC7 MWAC6 movlw 0x06 Cpfseq OPREG1 ; Test SubFunction 6 return call RESETADC ; Reset ADC bra WAC7 WAC6 movwf SHIFTREG call WRADC WAC7 movlw 0x01 movwf TXB0DLC,1 ; Data Length Code movff RECBYTE0,TXB0D0 ; Store Data in Transmit Buffer bsf TXB0CON,3,1 ; Start Transmission return WRADC: ; Writes at first to the Communication Register (8 Bit) ; and then to the selected Register (16 Bit) bsf LATE,2,0 ; Ser. Clock = 1 bcf LATC,0,0 ; /ADCSEL = 0 call ADCSHIFTO bsf LATC,0,0 ; /ADCSEL = 1 1. Transfer completed bcf LATC,0,0 ; /ADCSEL = 0 movff SHIFTREGH,SHIFTREG call ADCSHIFTO movff SHIFTREGL,SHIFTREG call ADCSHIFTO bsf LATC,0,0 ; /ADCSEL = 1 2. Transfer completed bcf LATE,2,0 ; Ser. Clock = 0 return ADCSHIFTO: ; Shifts n Bits to the ADC. n is stored in BITNUM movlw 0x08 movwf BITCNT ; 8 Bits to be shifted ASHIFT1 bcf LATE,2,0 ; Ser. Clock = 0 rlcf SHIFTREG ; Rotate left through Carry bc ASHIFT2 ; Branch if Carra set bcf LATE,1,0 ; Data Bit = 0 bra ASHIFT3 ASHIFT2 bsf LATE,1,0 ; Data Bit = 1 ASHIFT3 bsf LATE,2,0 ; Ser. Clock = 1 decfsz BITCNT bra ASHIFT1 return ;***************************************************************************** READADCCON: ; Response to Function 4: Read ADC Control Registers movlw 0x01 cpfseq OPREG1 ; Test SubFunction 1 bra MRAC2 RAC1: ; Read Status Register bcf BYTEFLAG,0,0 ; one Byte movlw 0x40 ; Address of Status Regsiter bra RAC7 MRAC2 movlw 0x02 Cpfseq OPREG1 ; Test SubFunction 2 bra MRAC3 RAC2: ; Read Mode Register bsf BYTEFLAG,0,0 ; two Bytes movlw 0x48 ; Address of Mode Regsiter bra RAC7 MRAC3 movlw 0x03 Cpfseq OPREG1 ; Test SubFunction 3 bra MRAC4 RAC3: ; Read Configuration Register bsf BYTEFLAG,0,0 ; two Bytes movlw 0x50 ; Address of Offset Regsiter bra RAC7 MRAC4 movlw 0x04 Cpfseq OPREG1 ; Test SubFunction 4 bra MRAC5 RAC4: ; Read ID Register bcf BYTEFLAG,0,0 ; one Byte movlw 0x60 ; Address of ID Regsiter bra RAC7 MRAC5 movlw 0x05 Cpfseq OPREG1 ; Test SubFunction 5 bra MRAC6 RAC5: ; Read Offset Register bsf BYTEFLAG,0,0 ; two Bytes movlw 0x70 ; Address of Offset Regsiter bra RAC7 MRAC6 movlw 0x06 Cpfseq OPREG1 ; Test SubFunction 6 bra MRAC7 RAC6: ; Read Full-Scale Register bsf BYTEFLAG,0,0 ; two Bytes movlw 0x78 ; Address of Full-Scale Regsiter bra RAC7 MRAC7 movlw 0x07 cpfseq OPREG1 ; Test SubFunction 7 return movff PERIOD,TXB0D1 ; Send Time Period movlw 0x02 movwf TXB0DLC,1 ; Data Length Code bra RAC8 RAC7 movwf SHIFTREG call RADC movff SHIFTREGL,TXB0D1 movff SHIFTREGH,TXB0D2 movlw 0x02 btfsc BYTEFLAG,0,0 ; one or two Bytes? movlw 0x03 movwf TXB0DLC,1 ; Data Length Code RAC8 movff RECBYTE0,TXB0D0 ; Store Data in Transmit Buffer bsf TXB0CON,3,1 ; Start Transmission return RADC: ; Reads one or two bytes from ADC Control Register bsf LATE,2,0 ; Ser. Clock = 1 bcf LATC,0,0 ; /ADCSEL = 0 RADC1 call ADCSHIFTO call ADCSHIFTI ; Shift in one byte btfsc BYTEFLAG,0,0 ; skip if one byte to be read bra RADC2 movff SHIFTREG,SHIFTREGL bra RADC3 RADC2 movff SHIFTREG,SHIFTREGH call ADCSHIFTI movff SHIFTREG,SHIFTREGL RADC3 nop ; bsf LATC,0,0 ; /ADCSEL = 1 Read Transfer completed ; bcf LATE,2,0 ; Ser. Clock = 0 return ADCSHIFTI: ; Shifts in one byte from ADC clrf SHIFTREG,0 movlw 0x08 movwf BITCNT ; 8 Bits to be shifted ADCSHI1 bcf LATE,2,0 ; Ser. Clock = 0 rlncf SHIFTREG,1,0 movff PORTE,OPREG bsf LATE,2,0 ; Ser. Clock = 1 btfsc OPREG,0,0 bra ADCSHI2 ; Branch if Bit set bcf SHIFTREG,0,0 bra ADCSHI3 ADCSHI2 bsf SHIFTREG,0,0 ADCSHI3 decfsz BITCNT bra ADCSHI1 return ;***************************************************************************** READADC: ; Response to Function 5: Read ADC movlw 0x01 cpfseq OPREG1 ; Test SubFunction 1 bra RAD2 bra ADC01 RAD2 movlw 0x02 Cpfseq OPREG1 ; Test SubFunction 2 bra RAD3 bra ADC23 RAD3 movlw 0x03 Cpfseq OPREG1 ; Test SubFunction 3 bra RAD4 bra ADC45 RAD4 movlw 0x04 Cpfseq OPREG1 ; Test SubFunction 4 bra RAD5 bra ADC67 RAD5 movlw 0x05 cpfseq OPREG1 ; Test SubFunction 5 bra RAD6 bra ADC89 RAD6 movlw 0x06 Cpfseq OPREG1 ; Test SubFunction 6 bra RAD7 bra ADCAB RAD7 movlw 0x07 Cpfseq OPREG1 ; Test SubFunction 7 bra RAD8 bra ADCCD RAD8 movlw 0x08 Cpfseq OPREG1 ; Test SubFunction 8 bra RAD9 bra ADCEF RAD9 return ADC01: ; Read ADC Channel 0 & 1 movff ASTAT0,TXB0D1 movff ADC0L,TXB0D2 movff ADC0H,TXB0D3 movff ASTAT1,TXB0D4 movff ADC1L,TXB0D5 movff ADC1H,TXB0D6 bra ADCFIN ADC23: ; Read ADC Channel 0 & 1 movff ASTAT2,TXB0D1 movff ADC2L,TXB0D2 movff ADC2H,TXB0D3 movff ASTAT3,TXB0D4 movff ADC3L,TXB0D5 movff ADC3H,TXB0D6 bra ADCFIN ADC45: ; Read ADC Channel 0 & 1 movff ASTAT4,TXB0D1 movff ADC4L,TXB0D2 movff ADC4H,TXB0D3 movff ASTAT5,TXB0D4 movff ADC5L,TXB0D5 movff ADC5H,TXB0D6 bra ADCFIN ADC67: ; Read ADC Channel 0 & 1 movff ASTAT6,TXB0D1 movff ADC6L,TXB0D2 movff ADC6H,TXB0D3 movff ASTAT7,TXB0D4 movff ADC7L,TXB0D5 movff ADC7H,TXB0D6 bra ADCFIN ADC89: ; Read ADC Channel 0 & 1 movff ASTAT8,TXB0D1 movff ADC8L,TXB0D2 movff ADC8H,TXB0D3 movff ASTAT9,TXB0D4 movff ADC9L,TXB0D5 movff ADC9H,TXB0D6 bra ADCFIN ADCAB: ; Read ADC Channel 0 & 1 movff ASTAT10,TXB0D1 movff ADC10L,TXB0D2 movff ADC10H,TXB0D3 movff ASTAT11,TXB0D4 movff ADC11L,TXB0D5 movff ADC11H,TXB0D6 bra ADCFIN ADCCD: ; Read ADC Channel 0 & 1 movff ASTAT12,TXB0D1 movff ADC12L,TXB0D2 movff ADC12H,TXB0D3 movff ASTAT13,TXB0D4 movff ADC13L,TXB0D5 movff ADC13H,TXB0D6 bra ADCFIN ADCEF: ; Read ADC Channel 0 & 1 movff ASTAT14,TXB0D1 movff ADC14L,TXB0D2 movff ADC14H,TXB0D3 movff ASTAT15,TXB0D4 movff ADC15L,TXB0D5 movff ADC15H,TXB0D6 ADCFIN movff RECBYTE0,TXB0D0 movlw 0x07 movwf TXB0DLC,1 ; Data Length Code bsf TXB0CON,3,1 ; Start Transmission return ;***************************************************************************** STATREAD: ; Response to Function 6: Read Status ; Tests the Argument Nr., and according to it the requested data are sent movlw 0x01 cpfseq OPREG1 ; Test SubFunction 1 bra STARG2 CANREAD: movlw 0x04 movwf TXB0DLC,1 ; Data Length Code movff RECBYTE0,TXB0D0 ; Store Data in Transmit Buffer movff COMSTAT,TXB0D1 movff TXERRCNT,TXB0D2 movff RXERRCNT,TXB0D3 bsf TXB0CON,3,1 ; Start Transmission return STARG2: movlw 0x02 cpfseq OPREG1 ; Test SubFunction 2 return VERSREAD: movlw 0x03 movwf TXB0DLC,1 ; Data Length Code movff RECBYTE0,TXB0D0 ; Store Data in Transmit Buffer movff VERSHIGH,TXB0D1 movff VERSLOW,TXB0D2 bsf TXB0CON,3,1 ; Start Transmission return ;***************************************************************************** END